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W948D6FB / W948D2FB
256Mb Mobile LPDDR
7.13 Deep Power Down
The Deep Power-Down (DPD) mode enables very low standby currents. All internal voltage generators inside the
LPDDR SDRAM are stopped and all memory data is lost in this mode. All the information in the Mode Register and
the Extended Mode Register is lost.
Deep Power-Down is entered using the BURST TERMINATE command except that CKE is registered Low. All
banks must be in idle state with no activity on the data bus prior to entering the DPD mode. While in this state, CKE
must be held in a constant Low state.
To exit the DPD mode, CKE is taken high after the clock is stable and NOP commands must be maintained for at
least 200 μ s. After 200 μ s a complete re-initialization is required following steps 4 through 11 as defined for the
initialization sequence.
7.13.1 Deep Power-Down Entry and Exit
T0
T1
Ta0
Ta1
Ta2
CK
CK
CKE
Command
NOP
DPD
NOP
Valid
Address
DQS
DQ
DM
t RP
Enter DPD
Mode
T=200us
Exit DPD
Mode
Valid
1) Clock must be stable before exiting Deep Power-Down mode. That is, the clock must be cycling
= Don't Care
within specifications by Ta0
2) Device must be in the all banks idle state prior to entering Deep Power-Down mode
3) 200us is required before any command can be applied upon exiting Deep-Down mode
4) Upon exiting Deep Power-Down mode a PRECHARGE ALL command must be issued, followed
by two REFRESH commands and a load mode register sequence
Publication Release Date : Oct, 15, 2012
- 44 -
Revision : A01-004
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